Capacitor fabrication methods and capacitor constructions

ABSTRACT

A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer, a chemisorption product of the first and second precursor layers being comprised by a layer of a conductive barrier material. The barrier layer may be sufficiently thick and dense to reduce oxidation of the first electrode by oxygen diffusion from over the barrier layer. An alternative method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer. The method may further include forming rugged polysilicon over the substrate, the first electrode being over the rugged polysilicon. Accordingly, the outer surface area of the first electrode can be at least 30% greater than the outer surface area of the substrate without the first electrode including polysilicon.

TECHNICAL FIELD

The aspects of the invention relate to capacitor fabrication methodsincluding forming conductive barrier layers and capacitor constructionshaving conductive barrier layers.

BACKGROUND OF THE INVENTION

Capacitors are common devices used in electronics, such as integratedcircuits, and particularly semiconductor-based technologies. Two commoncapacitor structures include metal-insulator-metal (MIM) capacitors andmetal-insulator-semiconductor (MIS) capacitors. One important factor toconsider when selecting a capacitor structure may be the capacitance perunit area. MIS capacitors may be advantageous since a first electrode asthe semiconductor may be formed of hemispherical grain (HSG) polysiliconthat exhibits a higher surface area in a given region compared to aplanar surface of amorphous silicon. The higher surface area providesmore capacitance per unit area occupied by a capacitor.

However, a high K factor (also known as dielectric constant or “κ”)dielectric material may be desirable to further enhance capacitance.Ta₂O₅ is one example of a high K factor dielectric, but it inherentlyforms an interfacial dielectric layer of SiO₂ when formed on a capacitorelectrode comprising HSG. The interfacial dielectric exhibits a lower Kfactor than Ta₂O₅ and thus reduces the effective dielectric constant forthe capacitor construction. Such reduction may be significant enough toeliminate any gain in capacitance per unit area otherwise achieved byusing HSG instead of a planar electrode. Use of other oxygen containinghigh K dielectric materials has proved to create similar problems.

Because it may be desirable to provide area enhancement of an electrodein a MIM structure using HSG, one attempt at addressing the statedproblem is forming a silicon nitride insulative barrier layer over theHSG. The silicon nitride barrier layer may be formed by nitridizing thesilicon of the outer surface of HSG. Unfortunately, silicon nitrideexhibits a K factor of only about 7, less than the K factor of some highK factor dielectrics that are desirable. Accordingly, even the siliconnitride barrier layer reduces the effective dielectric constant of thecapacitor.

SUMMARY OF THE INVENTION

In one aspect of the invention, a capacitor fabrication method mayinclude forming a first capacitor electrode over a substrate and atomiclayer depositing a conductive barrier layer to oxygen diffusion over thefirst electrode. A capacitor dielectric layer may be formed over thefirst electrode and a second capacitor electrode may be formed over thedielectric layer.

Another aspect of the invention may include chemisorbing a layer of afirst precursor at least one monolayer thick over the first electrodeand chemisorbing a layer of a second precursor at least one monolayerthick on the first precursor layer, a chemisorption product of the firstand second precursor layers being comprised by a layer of a conductivebarrier material.

Also, in another aspect of the invention a capacitor fabrication methodmay include forming a first capacitor electrode over a substrate. Thefirst electrode can have an inner surface area per unit area and anouter surface area per unit area that are both greater than an outersurface area per unit area of the substrate. A capacitor dielectriclayer may be formed over the first electrode and a second capacitorelectrode may be formed over the dielectric layer.

A still further aspect includes a capacitor fabrication method offorming an opening in an insulative layer over a substrate, the openinghaving sides and a bottom, forming a layer of polysilicon over the sidesand bottom of the opening, and removing the polysilicon layer from overthe bottom of the opening. At least some of the polysilicon layer may beconverted to hemispherical grain polysilicon. A first capacitorelectrode may be conformally formed on the converted polysilicon, thefirst electrode being sufficiently thin that the first electrode has anouter surface area per unit area greater than an outer surface area perunit area of the substrate underlying the first electrode. A capacitordielectric layer may be formed over the first electrode and a secondcapacitor electrode may be formed over the dielectric layer.

Other aspects of the invention include the capacitor constructionsformed from the above described methods.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

FIG. 1 is an enlarged view of a section of a semiconductor wafer at oneprocessing step in accordance with the invention.

FIG. 2 is an enlarged view of the section of the FIG. 1 wafer at aprocessing step subsequent to that depicted by FIG. 1.

FIG. 3 is an enlarged view of the section of the FIG. 1 wafer at aprocessing step subsequent to that depicted by FIG. 2.

FIG. 4 is an enlarged view of the section of the FIG. 1 wafer at aprocessing step subsequent to that depicted by FIG. 3.

FIG. 5 is an enlarged view of the section of the FIG. 1 wafer at aprocessing step subsequent to that depicted by FIG. 4.

FIG. 6 is an enlarged view of the section of the FIG. 1 wafer at aprocessing step subsequent to that depicted by FIG. 5.

FIG. 7 is an enlarged view of the section of the FIG. 1 wafer at analternate embodiment processing step subsequent to that depicted by FIG.2 in accordance with alternate aspects of the invention.

FIG. 8 is an enlarged view of the section of the FIG. 1 wafer at aprocessing step subsequent to that depicted by FIG. 7.

FIG. 9 is an enlarged view of the section of the FIG. 1 wafer at aprocessing step subsequent to that depicted by FIG. 8.

FIG. 10 is an enlarged view of the section of the FIG. 1 wafer at aprocessing step subsequent to that depicted by FIG. 9.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of theconstitutional purposes of the U.S. Patent Laws “to promote the progressof science and useful arts” (Article 1, Section 8).

Atomic layer deposition (ALD) involves formation of successive atomiclayers on a substrate. Such layers may comprise an epitaxial,polycrystalline, amorphous, etc. material. ALD may also be referred toas atomic layer epitaxy, atomic layer processing, etc. Further, theinvention may encompass other deposition methods not traditionallyreferred to as ALD, for example, chemical vapor deposition (CVD), butnevertheless including the method steps described herein. The depositionmethods herein may be described in the context of formation on asemiconductor wafer. However, the invention encompasses deposition on avariety of substrates besides semiconductor substrates.

In the context of this document, the term “semiconductor substrate” or“semiconductive substrate” is defined to mean any constructioncomprising semiconductive material, including, but not limited to, bulksemiconductive materials such as a semiconductive wafer (either alone orin assemblies comprising other materials thereon), and semiconductivematerial layers (either alone or in assemblies comprising othermaterials). The term “substrate” refers to any supporting structure,including, but not limited to, the semiconductive substrates describedabove.

Described in summary, ALD includes exposing an initial substrate to afirst chemical species to accomplish chemisorption of the species ontothe substrate. Theoretically, the chemisorption forms a monolayer thatis uniformly one atom or molecule thick on the entire exposed initialsubstrate. In other words, a saturated monolayer. Practically, asfurther described below, chemisorption might not occur on all portionsof the substrate. Nevertheless, such an imperfect monolayer is still amonolayer in the context of this document. In many applications, merelya substantially saturated monolayer may be suitable. A substantiallysaturated monolayer is one that will still yield a deposited layerexhibiting the quality and/or properties desired for such layer.

The first species is purged from over the substrate and a secondchemical species is provided to chemisorb onto the first monolayer ofthe first species. The second species is then purged and the steps arerepeated with exposure of the second species monolayer to the firstspecies. In some cases, the two monolayers may be of the same species.Also, a third species or more may be successively chemisorbed and purgedjust as described for the first and second species.

Purging may involve a variety of techniques including, but not limitedto, contacting the substrate and/or monolayer with a carrier gas and/orlowering pressure to below the deposition pressure to reduce theconcentration of a species contacting the substrate and/or chemisorbedspecies. Examples of carrier gases include N₂, Ar, He, Kr, Ne, Xe, etc.Purging may instead include contacting the substrate and/or monolayerwith any substance that allows chemisorption byproducts to desorb andreduces the concentration of a contacting species preparatory tointroducing another species. A suitable amount of purging can bedetermined experimentally as known to those skilled in the art. Purgingtime may be successively reduced to a purge time that yields an increasein film growth rate. The increase in film growth rate might be anindication of a change to a non-ALD process regime and may be used toestablish a purge time limit.

ALD is often described as a self-limiting process, in that a finitenumber of sites exist on a substrate to which the first species may formchemical bonds. The second species might only bond to the first speciesand thus may also be self-limiting. Once all of the finite number ofsites on a substrate are bonded with a first species, the first specieswill often not bond to other of the first species already bonded withthe substrate. However, process conditions can be varied in ALD topromote such bonding and render ALD not self-limiting. Accordingly, ALDmay also encompass a species forming other than one monolayer at a timeby stacking of a species, forming a layer more than one atom or moleculethick. The various aspects of the present invention described herein areapplicable to any circumstance where ALD may be desired.

Often, traditional ALD occurs within an often-used range of temperatureand pressure and according to established purging criteria to achievethe desired formation of an overall ALD layer one monolayer at a time.Even so, ALD conditions can vary greatly depending on the particularprecursors, layer composition, deposition equipment, and other factorsaccording to criteria known by those skilled in the art. Maintaining thetraditional conditions of temperature, pressure, and purging minimizesunwanted reactions that may impact monolayer formation and quality ofthe resulting overall ALD layer. Accordingly, operating outside thetraditional temperature and pressure ranges may risk formation ofdefective monolayers.

The general technology of chemical vapor deposition (CVD) includes avariety of more specific processes, including, but not limited to,plasma enhanced CVD and others. CVD is commonly used to formnon-selectively a complete, deposited material on a substrate. Onecharacteristic of CVD is the simultaneous presence of multiple speciesin the deposition chamber that react to form the deposited material.Such condition is contrasted with the purging criteria for traditionalALD wherein a substrate is contacted with a single deposition speciesthat chemisorbs to a substrate or previously deposited species. An ALDprocess regime may provide a simultaneously contacted plurality ofspecies of a type or under conditions such that ALD chemisorption,rather than CVD reaction occurs. Instead of reacting together, thespecies may chemisorb to a substrate or previously deposited species,providing a surface onto which subsequent species may next chemisorb toform a complete layer of desired material. Under most CVD conditions,deposition occurs largely independent of the composition or surfaceproperties of an underlying substrate. By contrast, chemisorption ratein ALD might be influenced by the composition, crystalline structure,and other properties of a substrate or chemisorbed species. Otherprocess conditions, for example, pressure and temperature, may alsoinfluence chemisorption rate.

ALD, as well as other deposition methods and/or methods of formingconductive barrier layers may be useful in capacitor fabricationmethods. According to one aspect of the invention, a capacitorfabrication method includes forming a first capacitor electrode over asubstrate and atomic layer depositing a conductive barrier layer tooxygen diffusion over the first electrode. A capacitor dielectric layermay be formed over the first electrode and a second capacitor electrodemay be formed over the dielectric layer. At least one of the first orsecond capacitor electrodes may comprise polysilicon, preferablyhemispherical grain (HSG) polysilicon. The dielectric layer may compriseoxygen. Exemplary materials for the dielectric layer include, but arenot limited to, Ta₂O₅, ZrO₂, WO₃, Al₂O₃, HfO₂, barium strontium titanate(BST), or strontium titanate (ST).

Notably, the conductive barrier layer to oxygen diffusion formed overthe first electrode may provide the advantage of reducing oxidation ofthe electrode by oxygen diffusion from an oxygen source, for example,the dielectric layer. The dielectric layer may be formed over thebarrier layer, thus, the barrier layer may reduce oxygen diffusion tothe first capacitor electrode. Alternatively, such a barrier layer mayreduce oxygen diffusion from the first capacitor electrode or under thefirst capacitor electrode to the dielectric layer or second capacitorelectrode.

It follows then that the barrier layer may also be formed over thecapacitor dielectric layer with the second capacitor electrode over thebarrier layer such that the barrier layer reduces oxygen diffusion fromthe dielectric layer to the second electrode. Such positioning may alsoreduce oxygen diffusion from over the dielectric layer to the firstcapacitor electrode, for example, oxygen diffusion from the secondcapacitor electrode. Accordingly, one aspect of the invention mayinclude atomic layer depositing the barrier layer over the firstelectrode, forming the dielectric layer over the barrier layer, andatomic layer depositing another conductive barrier to oxygen diffusionover the dielectric layer.

Prior to the atomic layer depositing, it may be advantageous to cleanthe deposition substrate, for example, the first electrode. Cleaning maybe accomplished by a method comprising HF dip, HF vapor clean, or NF₃remote plasma. Such cleaning methods may be performed in keeping withthe knowledge of those skilled in the art. Likewise, forming the firstand second electrodes and dielectric layer may be accomplished bymethods known to those skilled in the art and may include atomic layerdeposition, but preferably other methods.

The atomic layer depositing of the barrier layer may occur at atemperature of from about 100 to about 600° C. and at a pressure of fromabout 0.1 to about 10 Torr. The dielectric layer may exhibit a K factorof greater than about 7 at 20° C. Examples of suitable materials for thebarrier layer include WN, WSiN, TaN, TiN, TiSiN, Pt, Pt alloys, Ir, Iralloys, Pd, Pd alloys, RuO_(x), or IrO_(x), as well as other materials.The barrier layer may have a thickness of from about 50 to about 500Angstroms or another thickness depending on the material properties.

One consideration in selecting a material for the barrier layer is thethickness and density of the barrier layer that will be sufficient toachieve a desired level of oxygen diffusion reduction. Another factor toevaluate is that the barrier layer might be considered to form a part ofa capacitor electrode when the barrier layer contacts one of the firstor second electrodes since the barrier layer is conductive. Accordingly,it may be advantageous to recalculate the desired dimensions of anelectrode contacted by the barrier layer accounting for the presence ofthe additional conductive material. Accordingly, a “conductive” materialas the term is used herein designates a material exhibiting aconductivity at 20° C. of greater than 10⁴ microOhm⁻¹ centimeter⁻¹, orpreferably greater than about 10¹² microOhm⁻¹ centimeter⁻¹. Notably,such definition expressly includes “semiconductive” material in therange of about 10⁴ to about 10¹² microOhm⁻¹ centimeter⁻¹. As analternative, a “conductive” material in the present context might beviewed as a material that does not substantially impact the capacitanceotherwise achieved without the material. Generally, an “insulative”material might produce a change in capacitance as such a barrier layer.

As another aspect of the present invention, a capacitor fabricationmethod may include forming a first capacitor electrode over a substrate,chemisorbing a layer of a first precursor at least one monolayer thickover the first electrode, and chemisorbing a layer of a second precursorat least one monolayer thick on the first precursor layer. Achemisorption product of the first and second precursor layers may becomprised by a layer of a conductive barrier material. Because thechemisorption product is comprised by the barrier layer, the barrierlayer may also include conductive barrier material that is not achemisorption product of the first and second precursor layers. Acapacitor dielectric layer may be formed over the first electrode and asecond capacitor electrode may be formed over the dielectric layer. Thevarious positions for the barrier layer discussed above are alsoapplicable to the present aspect of the invention.

In forming the chemisorption product of the first and second precursorlayers, the first and second precursor layers may each consistessentially of a monolayer. Further, the first and second precursorlayers may each comprise substantially saturated monolayers. The extentof saturation might not be complete and yet the barrier layer willnevertheless provide the desired properties. Thus, substantiallysaturated may be adequate. The first and second precursor may eachconsist essentially of only one chemical species. However, as describedabove, precursors may also comprise more than one chemical species.Preferably, the first precursor is different from the second precursor,although for some barrier layers, the first and second precursor will bethe same. Examples of pairs of first and second precursors include:WF₆/NH₃, TaCl₅/NH₃, TiCl₄/NH₃, tetrakis(dimethylamido)titanium/NH₃,ruthenium cyclopentadiene/H₂O, IrF₅/H₂O, organometallic Pt/H₂O. It isconceivable that more than one of the preceding pairs may comprise thefirst and second precursors, but preferably only one of the pairs.Additional alternating first and second precursor layers may bechemisorbed in keeping with the above aspect of the invention to achievea desired thickness for the barrier layer.

Although ALD and/or chemisorbing first and second precursors may besuitable for forming a barrier layer, other methods may also besuitable. Accordingly, a variety of barrier layer forming techniques maybe used in combination with techniques to increase electrode surfacearea to provide enhancement of capacitance per unit area.

In another aspect of the invention, a capacitor fabrication method caninclude forming a first capacitor electrode over a substrate where thefirst electrode has an inner surface area per unit area and an outersurface area per unit area that are both greater than an outer surfacearea per unit area of the substrate. One example of obtaining the innerand outer electrode surface areas involves further forming ruggedpolysilicon over the substrate and forming the first electrode over therugged polysilicon. The first electrode can also be formed on the ruggedpolysilicon. The rugged polysilicon can have a surface area per unitarea greater than the surface area per unit area of conventionallyformed polysilicon that is not converted to rugged polysilicon. Acapacitor dielectric layer and a second capacitor electrode may beformed over the first electrode to produce a capacitor construction.

The first electrode can comprise TiN, as well as other materials, andmay be deposited by ALD, CVD, and perhaps other methods. The ruggedpolysilicon can be HSG polysilicon and it can also be undoped. Thus, inthe present aspect a first electrode may be formed having an outersurface area at least 30% greater the substrate outer surface area.Advantageously, the first electrode need not comprise polysilicon toaccomplish the surface area enhancement. Further, it is conceivable thatthe first electrode can be formed over materials other than ruggedpolysilicon that provide enhanced surface area compared to the substrateunderlying the first electrode.

To achieve more preferred first electrode surface area, ruggedpolysilicon may be formed using a seed density sufficiently small toyield at least some spaced apart grains. Thus, forming subsequent layersof the capacitor does not fill the space between grains so much as toreduce the capacitance enhancement possible with the first electrode ofincreased surface area. Conventionally, HSG is formed to optimizesurface area with very closely positioned grains since a capacitorelectrode will consist of the HSG. In the present aspect of theinvention, less closely positioned grains may be formed than wouldprovide optimal surface area for rugged or HSG polysilicon since thefirst electrode can be formed on the polysilicon rather than consist ofthe polysilicon. The less closely position grains of the invention willprovide a greater outer surface area for the first electrode compared towhat HSG optimized for surface area would provide to a first electrodeformed on optimized HSG. Also, undoped grains of rugged polysilicon mayprovide the advantage of grain size being smaller than for doped grainssuch that a smaller capacitor container may be used.

FIGS. 1-6 exemplify the features of the various aspects of the inventiondescribed above, as well as other aspects of the invention. For example,according to another aspect of the invention, FIG. 1 shows wafer portion1 including a substrate 2 with an insulative layer 4 formed thereon. Acapacitor fabrication method may include forming an opening 16 ininsulative layer 4, the opening 16 having sides and a bottom. Althoughnot shown, the opening may expose an electrical contact in substrate 2for subsequent electrical linking with a capacitor electrode. Turning toFIG. 2, a layer of polysilicon 6 may be formed over the sides and bottomof the opening. Polysilicon layer 6 may then be removed from over thebottom of opening 16 and converted by low density seeding to an undopedrugged layer 8 comprising HSG polysilicon, as shown in FIG. 3. Ananisotropic spacer etch may be used to remove polysilicon, preferablybefore conversion, from over the bottom of the opening while leavingpolysilicon over the sides. Accordingly, no undoped polysilicon willexist between an electrical contact, such as a polysilicon or metalplug, in substrate 2 and a bottom capacitor electrode. If polysilicon ispresent at the bottom, it may cause high contact resistance or an openbetween the bottom electrode and the contact.

In FIG. 4, a first capacitor electrode 10 may be conformally formed onundoped polysilicon 8. First electrode 10 may be sufficiently thin thatit has an outer surface area per unit area greater than an outer surfacearea per unit area of the portion of substrate 2 underlying firstelectrode 10. For example, first electrode 10 may have a thickness offrom about 50 to about 500 Angstroms, preferably about 200 Angstroms. Acapacitor dielectric layer 12 may be formed on first electrode 10 asshown in FIG. 5. FIG. 6 shows excess portions of dielectric layer 12 anda subsequently formed second capacitor electrode layer 14 removed fromover insulative layer 4 to produce a capacitor construction.

Advantageously, first electrode 10 has an enhanced surface area yetmight not produce a SiO₂ interfacial dielectric with an oxygencontaining dielectric layer since first electrode 10 may comprisematerials other than polysilicon, for example, TiN. Accordingly, thebenefits of high K dielectrics, such as Ta₂O₅, may be maximized whilestill providing enhanced electrode surface area.

FIGS. 7-10 exemplify the features of the various aspects of theinvention described above pertaining to barrier layers, as well as otheraspects of the invention, according to an alternative process flow. Forexample, FIG. 7 shows wafer portion 1 of FIG. 2 including a substrate 2with insulative layer 4, opening 16 in insulative layer 4, andpolysilicon layer 6 converted to a first capacitor electrode 18comprising doped HSG polysilicon.

In FIG. 8, a conductive barrier layer 20 may be conformally formed onfirst electrode 18 by, for example, ALD. A capacitor dielectric layer 22may be formed on barrier layer 20. The barrier layer may be sufficientlythick and dense to reduce oxidation of electrode 18 by oxygen diffusionfrom over the barrier layer. One source of oxygen diffusion may bedielectric layer 22. FIG. 9 shows formation of a second capacitorelectrode 24 on dielectric layer 22. FIG. 10 shows excess portions ofbarrier layer 20, dielectric layer 22, and second electrode layer 24removed from over insulative layer 4 to form a capacitor construction.As described above, a barrier layer may also be formed over a dielectriclayer although not shown in the Figures.

In a still further alternative aspect of the invention, barrier layer 20may be removed from over insulative layer 4 prior to forming dielectriclayer 22. Chemical mechanical polishing is one example of a suitableremoval method for excess portions of barrier layer 20. However, such analternative is less preferred since the portion of first electrode 18planar with insulative layer 4 might be exposed during polishing and maycontact dielectric layer 22. At the point of contact, an SiO₂interfacial dielectric may form if first electrode 18 includes siliconand dielectric layer 22 includes oxygen.

In compliance with the statute, the invention has been described inlanguage more or less specific as to structural and methodical features.It is to be understood, however, that the invention is not limited tothe specific features shown and described, since the means hereindisclosed comprise preferred forms of putting the invention into effect.The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1-33. (canceled)
 34. A capacitor fabrication method comprising: forminga first capacitor electrode containing HSG polysilicon over a substrate;atomic layer depositing a conductive layer on and in physical contactwith the first electrode, the conductive layer having a thickness offrom about 50 to about 500 Angstroms and containing WN, WSiN, TaN, TiN,TiSiN, Pt, Pt alloys, Ir, Ir alloys, Pd, Pd alloys, RuO_(x), or IrO_(x);forming an oxygen-containing capacitor dielectric layer on and inphysical contact with the conductive layer, the dielectric layerincluding Ta₂O₅, ZrO₂, WO₃, Al₂O₃, HfO₂, barium strontium titanate, orstrontium titanate; and forming a second capacitor electrode over thedielectric layer.
 35. The method of claim 34 wherein the atomic layerdeposited conductive layer has a thickness of from about 200 to about500 Angstroms.
 36. The method of claim 34 further comprising cleaningthe first electrode prior to the atomic layer depositing by a methodcomprising HF dip, HF vapor clean, or NF₃ remote plasma.
 37. The methodof claim 34 wherein the atomic layer deposited conductive layer has athickness and a density effective to reduce oxidation of the firstelectrode by oxygen from over the conductive layer, including from thedielectric layer.
 38. The method of claim 34 wherein the substratecomprises a semiconductive wafer.
 39. The method of claim 34 wherein theatomic layer deposited conductive layer comprises WN.
 40. The method ofclaim 34 wherein the atomic layer deposited conductive layer comprisesTiN.
 41. The method of claim 34 wherein the capacitor dielectric layercomprises Al₂O₃.
 42. The method of claim 34 wherein the second capacitorelectrode comprises TiN.
 43. The method of claim 34 wherein the atomiclayer deposited conductive layer comprises TiN, the capacitor dielectriclayer comprises Al₂O₃, and the second capacitor electrode comprises TiN.44. The method of claim 34 wherein the atomic layer depositing occurs ata temperature of from about 100 to about 600° C. and at a pressure offrom about 0.1 to about 10 Torr.
 45. A capacitor fabrication methodcomprising: forming a first capacitor electrode containing polysiliconover a substrate; atomic layer depositing a conductive layer on and inphysical contact with the first electrode, the conductive layer having athickness of from about 200 to about 500 Angstroms and containing TiN;forming an oxygen-containing capacitor dielectric layer on and inphysical contact with the conductive layer, the dielectric layerincluding Ta₂O₅, ZrO₂, WO₃, Al₂O₃, HfO₂, barium strontium titanate, orstrontium titanate; and forming a second capacitor electrode on and inphysical contact with the dielectric layer, the second capacitorelectrode containing TiN.
 46. The method of claim 45 wherein thecapacitor dielectric layer comprises Al₂O₃.
 47. The method of claim 45wherein the substrate comprises a semiconductive wafer.
 48. The methodof claim 45 wherein the polysilicon comprises HSG polysilicon.
 49. Acapacitor fabrication method comprising: forming a first capacitorelectrode containing polysilicon over a substrate; atomic layerdepositing a conductive layer on and in physical contact with the firstelectrode, the conductive layer containing WN; forming anoxygen-containing capacitor dielectric layer on and in physical contactwith the conductive layer, the dielectric layer including Ta₂O₅, ZrO₂,WO₃, Al₂O₃, HfO₂, barium strontium titanate, or strontium titanate; andforming a second capacitor electrode on and in physical contact with thedielectric layer, the second capacitor electrode containing TiN.
 50. Themethod of claim 49 wherein the capacitor dielectric layer comprisesAl₂O₃.
 51. The method of claim 49 wherein the substrate comprises asemiconductive wafer.
 52. The method of claim 49 wherein the polysiliconcomprises HSG polysilicon.
 53. The method of claim 49 wherein the atomiclayer deposited conductive layer has a thickness of from about 200 toabout 500 Angstroms.